OMAP3 clock: add a short delay when lowering CORE clk rate

Browse source

When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize.  Without this delay, the system is prone to random
panics upon re-entering SDRAM.

This time delay varies based on MPU frequency.  At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

...

This commit is contained in:

Paul Walmsley 2009-06-19 19:08:26 -06:00 • committed by paul

parent 2f135eaf18

commit c9812d042a

4 changed files with 44 additions and 18 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

30

arch/arm/mach-omap2/clock34xx.c

View file

20

arch/arm/mach-omap2/sram34xx.S

View file

4

arch/arm/plat-omap/include/mach/sram.h

View file

8

arch/arm/plat-omap/sram.c

View file