DMA: shdma: support the new CHCLR register layout

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On newer r-car SoCs the CHCLR register only contains one bit per channel,
to which a 1 has to be written to reset the channel. Older SoC versions had
one CHCLR register per channel, to which a 0 must be written to reset the
channel and clear its buffers. This patch adds support for the newer
layout.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

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Guennadi Liakhovetski 2013-07-10 12:09:47 +02:00 • committed by Vinod Koul

parent 115357e977

commit ca8b387803

2 changed files with 45 additions and 3 deletions

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14

drivers/dma/sh/shdma.c

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34

include/linux/sh_dma.h

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