drm/amd/display: limit display clock to 100MHz to avoid FIFO error

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[Why]
when changing display clock, SMU need to use power up DFS and use
DENTIST to ramp DFS DID to switch target frequency before switching back
to bypass.

[How]
fixed the minimum display clock to 100MHz, it's W/A the same with PCO.

Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Yu-ting Shen 2020-02-07 15:19:31 +08:00 • committed by Alex Deucher

parent e2c9529f00

commit cab5dec425

2 changed files with 4 additions and 0 deletions

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3

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

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1

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

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