media: ccs-pll: Add support for lane speed model

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CCS PLL includes a capability to calculate the VT clocks on per-lane
basis. Add support for this feature.

Move calculation of the pixel rate on the CSI-2 bus early in the function
as everything needed to calculate it is already available.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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Sakari Ailus 2020-06-22 12:16:24 +02:00 • committed by Mauro Carvalho Chehab

parent e583e65456

commit cac8f5d28e

2 changed files with 31 additions and 11 deletions

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36

drivers/media/i2c/ccs-pll.c

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6

drivers/media/i2c/ccs-pll.h

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