perf, x86: Implement simple LBR support

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Implement simple suport Intel Last-Branch-Record, it supports all
hardware that implements FREEZE_LBRS_ON_PMI, but does not (yet) implement
the LBR config register.

The Intel LBR is a FIFO of From,To addresses describing the last few
branches the hardware took.

This patch does not add perf interface to the LBR, but merely provides an
interface for internal use.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.544191154@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

...

This commit is contained in:

Peter Zijlstra 2010-03-03 12:02:30 +01:00 • committed by Ingo Molnar

parent 69fef0d2e2

commit caff2befff

4 changed files with 270 additions and 0 deletions

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18

arch/x86/kernel/cpu/perf_event.c

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13

arch/x86/kernel/cpu/perf_event_intel.c

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228

arch/x86/kernel/cpu/perf_event_intel_lbr.c

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11

include/linux/perf_event.h

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