KVM: x86/mmu: Support shadowing NPT when 5-level paging is enabled in host

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When the 5-level page table CPU flag is set in the host, but the guest
has CR4.LA57=0 (including the case of a 32-bit guest), the top level of
the shadow NPT page tables will be fixed, consisting of one pointer to
a lower-level table and 511 non-present entries.  Extend the existing
code that creates the fixed PML4 or PDP table, to provide a fixed PML5
table if needed.

This is not needed on EPT because the number of layers in the tables
is specified in the EPTP instead of depending on the host CR4.

Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Message-Id: <20210818165549.3771014-3-wei.huang2@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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This commit is contained in:

Wei Huang 2021-08-18 11:55:48 -05:00 • committed by Paolo Bonzini

parent 746700d21f

commit cb0f722aff

2 changed files with 38 additions and 16 deletions

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arch/x86/include/asm/kvm_host.h

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53

arch/x86/kvm/mmu/mmu.c

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