clk: tegra20/30: Don't pre-initialize displays parent clock

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Both Tegra20 and Tegra30 are initializing display's parent clock
incorrectly because PLLP is running at 216/408MHz while display rate is
set to 600MHz, but pre-setting the parent isn't needed at all because
display driver selects proper parent anyways.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Dmitry Osipenko 2019-12-18 21:44:06 +03:00 • committed by Thierry Reding

parent cf83a28f28

commit cb98598e68

2 changed files with 0 additions and 4 deletions

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2

drivers/clk/tegra/clk-tegra20.c

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2

drivers/clk/tegra/clk-tegra30.c

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