drm/i915/display: fix level 0 adjustement on display ver >= 12

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We should no longer increment level 0 by 1usec when we have 16Gb DIMMs.
Instead spec says to add 3usec (as opposed to 2) to each valid level
when punit replies 0 to level 0.

So set wm_lv_0_adjust_needed to false for DISPLAY_VER() >= 12 and set
the proper adjustment value when handling WaWmMemoryReadLatency.

Bspec: 49326, 4381
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210622212210.3746133-1-lucas.demarchi@intel.com

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This commit is contained in:

Lucas De Marchi 2021-06-22 14:22:09 -07:00

parent c4449742a7

commit cbeeb00f14

2 changed files with 8 additions and 8 deletions

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3

drivers/gpu/drm/i915/intel_dram.c

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13

drivers/gpu/drm/i915/intel_pm.c

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