drm/amd/display: Allow asic specific FSFT timing optimization

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[Why]
Each asic can optimize best based on its capabilities

[How]
Optimizing timing for a new pixel clock

Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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This commit is contained in:

Reza Amini 2020-07-15 11:33:23 -04:00 • committed by Alex Deucher

parent 9b6ca29e09

commit cc0f379dd2

8 changed files with 57 additions and 13 deletions

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18

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

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4

drivers/gpu/drm/amd/display/dc/dc_stream.h

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27

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

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5

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h

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3

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c

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3

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c

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5

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

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5

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

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