drm/i915/dp: Cache max common lane count

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Cache the maximum common lane count together with the common link
rates.

This is safe because the cached value is updated:
- during driver probe, before the connector is registered and can be
  used for mode validation or modesetting
- during resume, before output HW state readout can query it
- during connector detection, right after updating the sink/link
  capabilities

Caching the value allows detecting max common lane count changes in
a follow-up change and keeps the tracking of max common lane count
aligned with that of common rates.

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20260522160514.2628249-4-imre.deak@intel.com

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This commit is contained in:

Imre Deak 2026-05-22 19:05:13 +03:00

parent 0759e16078

commit cc18eac531

2 changed files with 9 additions and 2 deletions

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1

drivers/gpu/drm/i915/display/intel_display_types.h

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10

drivers/gpu/drm/i915/display/intel_dp.c

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