drm/amd/display: Fix DML2 logic to set clk state to min

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[Why]

When an eDP with high clock states is going into s0i3, stream_count is
0. This causes DML to not update the clks to the lowest state and
blocking us to enter s0i3 since eDP is out of vmin.

[How]

When stream_count is 0, set all the clocks to the lowest state.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Nicholas Susanto <nicholas.susanto@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Nicholas Susanto 2024-05-14 11:38:39 -04:00 • committed by Alex Deucher

parent c5afb313e7

commit cc4d6ea0f2

1 changed files with 17 additions and 1 deletions

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drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c

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