drm/sun4i: hdmi: Allow using second PLL as TMDS clk parent

Browse source

On SoCs with two display pipelines, it is possible that the two
pipelines are active at the same time, with potentially incompatible
dot clocks.

Let the HDMI encoder's TMDS clock go through all of its parents when
calculating possible clock rates. This allows usage of the second video
PLL as its parent.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-6-wens@csie.org

...

This commit is contained in:

Chen-Yu Tsai 2017-10-10 11:20:02 +08:00 • committed by Maxime Ripard

parent 4b1c924b1f

commit cc67ae90be

1 changed files with 29 additions and 24 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

45

drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c

View file