iio: frequency: ad9523: Fix alignment for DMA safety

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[ Upstream commit 8ff2eb625c ]

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Updated help text to 'may' require buffers to be in their own cacheline.

Fixes: cd1678f963 ("iio: frequency: New driver for AD9523 SPI Low Jitter Clock Generator")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-66-jic23@kernel.org
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Jonathan Cameron 2022-05-08 18:56:45 +01:00 • committed by Greg Kroah-Hartman

parent 33fcddee19

commit cc7b3068c7

1 changed files with 3 additions and 3 deletions

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drivers/iio/frequency/ad9523.c

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