clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type

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The variable PLL2 clock type was superseded by the more generic
variable fractional 8.25 PLL clock type, and its sole user was converted.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/8e5564958002351f29435f63de1304fb3b51a725.1721648548.git.geert+renesas@glider.be

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Geert Uytterhoeven 2024-07-22 13:50:33 +02:00

parent 2cf316b4c5

commit ccdf745bd1

2 changed files with 0 additions and 10 deletions

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9

drivers/clk/renesas/rcar-gen4-cpg.c

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1

drivers/clk/renesas/rcar-gen4-cpg.h

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