drm/i915/psr: Block DC3CO entry during active frame

Browse source

On Xe3P, when PSR2 is enabled on a panel that does not support
Early Transport, DC3CO can be entered in the middle of an
active frame. This prevents the pipe from completing the frame
and leaves it in a bad state that does not recover well,
causing visible corruption on screen.

Set CHICKEN_DCPR_4 bit 24 in the PSR2 enable path when Early Transport
is not in use, to notify DMC to prevent DC3CO entry.

v2:
- Remove display from commit header (Suraj Kandpal).
- Add HSD number to intel_display_wa framework (Suraj Kandpal).
- Change register prefix from XE3LPD_ to XE3P_ (Suraj Kandpal).

BSpec: 71483, 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260701100650.1689665-2-dibin.moolakadan.subrahmanian@intel.com

...

This commit is contained in:

Dibin Moolakadan Subrahmanian 2026-07-01 15:36:50 +05:30 • committed by Suraj Kandpal

parent b4ea527213

commit cd0121502c

4 changed files with 22 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

3

drivers/gpu/drm/i915/display/intel_display_regs.h

View file

2

drivers/gpu/drm/i915/display/intel_display_wa.c

View file

1

drivers/gpu/drm/i915/display/intel_display_wa.h

View file

16

drivers/gpu/drm/i915/display/intel_psr.c

View file