perf/x86/intel: Avoid rewriting DEBUGCTL with the same value for LBRs

Browse source

perf with LBRs on has a tendency to rewrite the DEBUGCTL MSR with
the same value. Add a little optimization to skip the unnecessary
write.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1426871484-21285-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>

...

This commit is contained in:

Andi Kleen 2015-03-20 10:11:24 -07:00 • committed by Ingo Molnar

parent 1a78d93750

commit cd1f11de69

1 changed files with 4 additions and 2 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

6

arch/x86/kernel/cpu/perf_event_intel_lbr.c

View file