pwm: mediatek: Fix PWM source clock selection

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In original code, the PWM output frequency is not correct when set
bit<3>=1 to PWMCON register.

Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

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Zhi Mao 2017-06-30 14:05:17 +08:00 • committed by Thierry Reding

parent aa12d7a7a9

commit cd30798a6c

1 changed files with 1 additions and 1 deletions

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drivers/pwm/pwm-mediatek.c

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