coresight tmc etr: Cleanup AXICTL register handling

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This patch cleans up how we setup the AXICTL register on
TMC ETR. At the moment we don't set the CacheCtrl bits, which
drives the arcache and awcache bits on AXI bus specifying the
cacheablitiy. Set this to Write-back Read and Write-allocate.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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Suzuki K Poulose 2017-08-02 10:22:14 -06:00 • committed by Greg Kroah-Hartman

parent ff11f5bc5a

commit cd407abd5e

2 changed files with 19 additions and 8 deletions

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10

drivers/hwtracing/coresight/coresight-tmc-etr.c

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17

drivers/hwtracing/coresight/coresight-tmc.h

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