clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210

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Introduce the low jitter path of PLLP and PLLMB which can be used as EMC
clock source.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Joseph Lo 2019-05-29 16:21:33 +08:00 • committed by Thierry Reding

parent 3dcbd36fa3

commit cd4d6f3575

2 changed files with 13 additions and 2 deletions

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11

drivers/clk/tegra/clk-tegra210.c

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4

include/dt-bindings/clock/tegra210-car.h

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