drm/i915: Write the FDI RX TU size reg at the right time

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According to "Graphics BSpec: vol4g North Display Engine Registers [IVB],
Display Mode Set Sequence" We need to write the TU size register
of the fdi RX unit _before_ starting to train the link.

Note: The current code is actually correct as Paulo mentioned in
review, but it's a bit confusion since only the fdi rx/tx plls need to
be enabled before the cpu pipes/planes. Hence it's still a good idea
to move the TU_SIZE setting to the "right" spot in the sequence, to
better match Bspec.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Daniel Vetter 2012-10-26 10:58:12 +02:00

parent 4a0833ec48

commit cd986abbac

1 changed files with 5 additions and 3 deletions

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drivers/gpu/drm/i915/intel_display.c

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