Samsung SoC clock drivers changes for 6.10

1. Allow choice of manual or firmware-driven control over PLLs, needed
    to fully implement CPU clock controllers on Exynos850.
 
 2. Correct PLL clock IDs on ExynosAutov9.
 
 3. Google GS101:
    - Propagate certain clock rates to allow setting proper SPI clock
      rates.
    - Add HSI0 and HSI2 clock controllers.
    - Mark certain clocks critical.
 
 4. Convert old S3C64xx clock controller bindings to DT schema.
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Merge tag 'samsung-clk-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung clk driver updates from Krzysztof Kozlowski:

 - Allow choice of manual or firmware-driven control over PLLs, needed
   to fully implement CPU clock controllers on Exynos850
 - Correct PLL clock IDs on ExynosAutov9
 - Propagate certain clock rates to allow setting proper SPI clock
   rates on Google GS101
 - Add HSI0 and HSI2 clock controllers for Google GS101
 - Mark certain Google GS101 clocks critical
 - Convert old S3C64xx clock controller bindings to DT schema

* tag 'samsung-clk-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: gs101: drop unused HSI2 clock parent data
  clk: samsung: gs101: mark some apm UASC and XIU clocks critical
  clk: samsung: gs101: add support for cmu_hsi2
  clk: samsung: gs101: add support for cmu_hsi0
  dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
  dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit
  clk: samsung: gs101: propagate PERIC1 USI SPI clock rate
  clk: samsung: gs101: propagate PERIC0 USI SPI clock rate
  clk: samsung: exynosautov9: fix wrong pll clock id value
  dt-bindings: clock: samsung,s3c6400-clock: convert to DT Schema
  clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1
  clk: samsung: Implement manual PLL control for ARM64 SoCs
This commit is contained in:
Stephen Boyd 2024-05-08 18:15:23 -07:00
commit ce68962854
9 changed files with 1807 additions and 208 deletions