drm/amd/display: Fix DP2.0 timing sync

Browse source

[Why]
Triggering OTG sync before all OTG/HPO clock programming is complete
causes timing sync to fail and a subsequent P-state hang.

[How]
Move DTB clock programming earlier in the sequence to
enable_stream_timing.

Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Ilya Bakoulin <ilya.bakoulin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Ilya Bakoulin 2023-09-07 14:03:15 -04:00 • committed by Alex Deucher

parent 1288d70208

commit ce74bece80

5 changed files with 55 additions and 31 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

79

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

View file

1

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c

View file

1

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c

View file

1

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c

View file

4

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

View file