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cxgb4/cxgb4vf: For T5 use Packing and Padding Boundaries for SGE DMA transfers

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T5 introduces the ability to have separate Packing and Padding Boundaries
for SGE DMA transfers from the chip to Host Memory. This change set takes
advantage of that to set up a smaller Padding Boundary to conserve PCI Link
and Memory Bandwidth with T5.

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Hariprasad Shenai 2014-11-07 17:06:30 +05:30 • committed by David S. Miller
commit ce8f407a3c
6 changed files with 135 additions and 11 deletions
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