clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0

Browse source

Add a workaround for errata on R-Car H3 ES1.0, where the PLL0, PLL2, and
PLL4 clock frequencies are off by a factor of two.

Inspired by a patch by Dien Pham in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Dien Pham <dien.pham.ry@renesas.com>

...

This commit is contained in:

Geert Uytterhoeven 2017-03-10 11:46:10 +01:00

parent 5f3a432a44

commit cecbe87d73

1 changed files with 24 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

24

drivers/clk/renesas/rcar-gen3-cpg.c

View file