crypto: x86/chacha20 - Add a 8-block AVX-512VL variant

Browse source

This variant is similar to the AVX2 version, but benefits from the AVX-512
rotate instructions and the additional registers, so it can operate without
any data on the stack. It uses ymm registers only to avoid the massive core
throttling on Skylake-X platforms. Nontheless does it bring a ~30% speed
improvement compared to the AVX2 variant for random encryption lengths.

The AVX2 version uses "rep movsb" for partial block XORing via the stack.
With AVX-512, the new "vmovdqu8" can do this much more efficiently. The
associated "kmov" instructions to work with dynamic masks is not part of
the AVX-512VL instruction set, hence we depend on AVX-512BW as well. Given
that the major AVX-512VL architectures provide AVX-512BW and this extension
does not affect core clocking, this seems to be no problem at least for
now.

Signed-off-by: Martin Willi <martin@strongswan.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

...

This commit is contained in:

Martin Willi 2018-11-20 17:30:48 +01:00 • committed by Herbert Xu

parent 059c2a4d8e

commit cee7a36ecb

3 changed files with 427 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

5

arch/x86/crypto/Makefile

View file

396

arch/x86/crypto/chacha20-avx512vl-x86_64.S

View file

26

arch/x86/crypto/chacha20_glue.c

View file