MIPS: cpu-probe: Set the FTLB probability bit on supported cores

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Make use of the Config6/FLTBP bit to set the probability of a TLBWR
instruction to hit the FTLB or the VTLB. A value of 0 (which may be
the default value on certain cores, such as proAptiv or P5600)
means that a TLBWR instruction will never hit the VTLB which
leads to performance limitations since it effectively decreases
the number of available TLB slots.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8368/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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Markos Chandras 2014-11-10 12:25:34 +00:00 • committed by Ralf Baechle

parent 4ec8f9e9b0

commit cf0a8aa022

2 changed files with 34 additions and 1 deletions

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arch/mips/include/asm/mipsregs.h

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33

arch/mips/kernel/cpu-probe.c

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