clk: meson: axg-audio: provide clk top signal name

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The peripheral clock on the sm1 goes through some muxes
and dividers before reaching the audio gates. To model that,
without repeating our self too much, the "top" clock signal
is introduced and will serve as a the parent of the gates.

On the axg and g12a, the top clock is just a pass-through to
the audio peripheral clock provided by the main controller.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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This commit is contained in:

Jerome Brunet 2019-10-02 11:15:28 +02:00

parent 8ff93f2832

commit cf52db456f

2 changed files with 17 additions and 4 deletions

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18

drivers/clk/meson/axg-audio.c

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3

drivers/clk/meson/axg-audio.h

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