phy: qcom-qmp-pcie: Fix sm8450_qmp_gen4x2_pcie_pcs_tbl[] register names

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[ Upstream commit 883aebf6e1 ]

sm8450_qmp_gen4x2_pcie_pcs_tbl[] contains the init sequence for PCS
registers of QMP PHY v5.20. So use the v5.20 specific register names.
Only major change is the rename of PCS_EQ_CONFIG{2/3} registers to
PCS_EQ_CONFIG{4/5}.

Fixes: 2c91bf6bf2 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20221102081835.41892-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Manivannan Sadhasivam 2022-11-02 13:48:35 +05:30 • committed by Greg Kroah-Hartman

parent c5ca087f47

commit cf66351484

3 changed files with 19 additions and 4 deletions

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8

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

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14

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h

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1

drivers/phy/qualcomm/phy-qcom-qmp.h

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