drm/nouveau/falcon: fix base address of FBIF registers

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All falcons have their FBIF registers starting at offset 0x600, with the
exception of the PMU and NVENC engines.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

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Alexandre Courbot 2017-01-26 16:49:43 +09:00 • committed by Ben Skeggs

parent ad147b7f57

commit cfd044b028

1 changed files with 20 additions and 5 deletions

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drivers/gpu/drm/nouveau/nvkm/falcon/v1.c

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