arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk

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The PCIe Gen4x2 PHY found in the SM8650 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.

Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes
2 clocks, properly add the pcie1_phy provided clocks to the Global Clock
Controller (GCC) node clocks inputs.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-3-10c650cfeade@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

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Neil Armstrong 2024-05-02 10:00:38 +02:00 • committed by Bjorn Andersson

parent 0cc97d9e3f

commit d00b42f170

3 changed files with 4 additions and 17 deletions

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4

arch/arm64/boot/dts/qcom/sm8650-mtp.dts

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arch/arm64/boot/dts/qcom/sm8650-qrd.dts

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arch/arm64/boot/dts/qcom/sm8650.dtsi

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