drm/msm/a6xx: Fix A621 GPUCC register list for state capture

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A621 uses an incorrect GPUCC register list during state capture.

The existing list matches A623/A663. Rename it accordingly and add a
dedicated A621 GPUCC register list.

Fixes: 11cdb81b3c ("drm/msm/a6xx: Fix gpucc register block for A621")
Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/730659/
Message-ID: <20260605-assorted-fixes-june-v1-4-2caa04f7287c@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

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This commit is contained in:

Jie Zhang 2026-06-05 01:38:20 +05:30 • committed by Rob Clark

parent fc7ccbc617

commit d052d0358f

2 changed files with 16 additions and 3 deletions

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7

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

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12

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

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