clk: imx8mp: remove SYS PLL 1/2 clock gates

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Remove the PLL 1/2 gates as it make AMP clock management harder without
obvious benifit.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220225081733.2294166-4-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

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Peng Fan 2022-02-25 16:17:33 +08:00 • committed by Abel Vesa

parent 38ce00adc1

commit d097cc045b

1 changed files with 16 additions and 32 deletions

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48

drivers/clk/imx/clk-imx8mp.c

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