arm64/perf: Add Cavium ThunderX PMU support

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Support PMU events on Caviums ThunderX SOC. ThunderX supports
some additional counters compared to the default ARMv8 PMUv3:

- branch instructions counter
- stall frontend & backend counters
- L1 dcache load & store counters
- L1 icache counters
- iTLB & dTLB counters
- L1 dcache & icache prefetch counters

Signed-off-by: Jan Glauber <jglauber@cavium.com>
[will: capitalisation]
Signed-off-by: Will Deacon <will.deacon@arm.com>

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Jan Glauber 2016-02-18 17:50:11 +01:00 • committed by Will Deacon

parent 5f140ccef3

commit d0aa2bffcf

1 changed files with 68 additions and 1 deletions

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arch/arm64/kernel/perf_event.c

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