oprofile/x86: reserve counter msrs pairwise

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For AMD's and Intel's P6 generic performance counters have pairwise
counter and control msrs. This patch changes the counter reservation
in a way that both msrs must be registered. It joins some counter
loops and also removes the unnecessary NUM_CONTROLS macro in the AMD
implementation.

Signed-off-by: Robert Richter <robert.richter@amd.com>

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Robert Richter 2010-03-23 19:33:21 +01:00

parent 8f5a2dd83a

commit d0e4120fda

2 changed files with 36 additions and 43 deletions

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43

arch/x86/oprofile/op_model_amd.c

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36

arch/x86/oprofile/op_model_ppro.c

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