drm/amdgpu: add uvd enc registers in header

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Add UVD encode write/read/size/base registers definition for uvd6.3 HEVC ecoding

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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James Zhu 2017-10-01 20:00:07 -04:00 • committed by Alex Deucher

parent 4b6aca2f59

commit d0e62855fa

1 changed files with 15 additions and 0 deletions

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drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_d.h

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