clk: tegra: Fix PLLE programming

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PLLE has M, N and P divider shift and width parameters that differ from
the defaults. Furthermore, when clearing the M, N and P divider fields
the corresponding masks were never shifted, thereby clearing only the
lowest bits of the register. This lead to a situation where the PLLE
programming would only work if the register hadn't been touched before.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>

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Thierry Reding 2014-04-04 15:55:13 +02:00 • committed by Peter De Schrijver

parent c9eaa447e7

commit d0f02ce3b1

1 changed files with 24 additions and 6 deletions

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drivers/clk/tegra/clk-pll.c

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