agp/intel: fix cache control for sandybridge

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This is broken from 97ef1bdd0b.
Let's set the correct bit for LLC+MLC and LLC only.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

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Zhenyu Wang 2010-11-02 17:30:46 +08:00 • committed by Chris Wilson

parent 328fc1325f

commit d110852513

1 changed files with 2 additions and 2 deletions

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drivers/char/agp/intel-gtt.c

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