drm/amd/display: On clock init, maintain DISPCLK freq

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[Description]
- On init if a display is connected, we need to maintain the DISPCLK
  frequency
- Even though DPG_EN=1, the display still requires the correct
  timing or it could cause audio corruption (if DISPCLK freq
  is reduced)
- Read the current DISPCLK freq and request the same value to ensure
  the timing is valid and unchanged
- However, add option to do a full pipe power down (including link)
  which will also avoid audio related issues
	- Disabled for the time being on dcn32

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Alvin Lee 2023-03-24 12:01:09 -04:00 • committed by Alex Deucher

parent 0289e0ed1b

commit d170e938f0

6 changed files with 45 additions and 5 deletions

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18

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

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1

drivers/gpu/drm/amd/display/dc/dc.h

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26

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

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1

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

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1

drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c

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3

drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h

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