arm64: erratum: Work around Falkor erratum #E1003 in trampoline code

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We rely on an atomic swizzling of TTBR1 when transitioning from the entry
trampoline to the kernel proper on an exception. We can't rely on this
atomicity in the face of Falkor erratum #E1003, so on affected cores we
can issue a TLB invalidation to invalidate the walk cache prior to
jumping into the kernel. There is still the possibility of a TLB conflict
here due to conflicting walk cache entries prior to the invalidation, but
this doesn't appear to be the case on these CPUs in practice.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Tested-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>

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Will Deacon 2017-11-14 14:29:19 +00:00

parent 4bf3286d29

commit d1777e686a

2 changed files with 17 additions and 12 deletions

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17

arch/arm64/Kconfig

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12

arch/arm64/kernel/entry.S

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