drm/i915/icl: Configure DSI transcoder timings

Browse source

As part of DSI enable sequence, transcoder timings
(horizontal & vertical) need to be set so that transcoder
will generate the stream output as per those timings.
This patch set required transcoder timings as per BSPEC.

v2: Remove TRANS_TIMING_SHIFT usage

v3 by Jani:
 - Rebase
 - Reduce temp variable use
 - Checkpatch fix

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/525949ae4e919a4f2b807d606234322534656048.1539613303.git.jani.nikula@intel.com

...

This commit is contained in:

Madhav Chauhan 2018-10-15 17:28:03 +03:00 • committed by Jani Nikula

parent 7b56caf363

commit d1aeb5f399

1 changed files with 118 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

118

drivers/gpu/drm/i915/icl_dsi.c

View file