KVM: PPC: Book3S HV: Don't access XIVE PIPR register using byte accesses

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The XIVE interrupt controller on POWER9 machines doesn't support byte
accesses to any register in the thread management area other than the
CPPR (current processor priority register).  In particular, when
reading the PIPR (pending interrupt priority register), we need to
do a 32-bit or 64-bit load.

Cc: stable@vger.kernel.org # v4.13
Fixes: 2c4fb78f78 ("KVM: PPC: Book3S HV: Workaround POWER9 DD1.0 bug causing IPB bit loss")
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

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Benjamin Herrenschmidt 2017-09-06 15:20:55 +10:00 • committed by Paul Mackerras

parent 5f54c8b2d4

commit d222af0723

3 changed files with 4 additions and 5 deletions

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1

arch/powerpc/kvm/book3s_hv_rm_xive.c

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arch/powerpc/kvm/book3s_xive.c

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7

arch/powerpc/kvm/book3s_xive_template.c

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