perf/x86/intel: Initialize architectural PEBS

Browse source

arch-PEBS leverages CPUID.23H.4/5 sub-leaves enumerate arch-PEBS
supported capabilities and counters bitmap. This patch parses these 2
sub-leaves and initializes arch-PEBS capabilities and corresponding
structures.

Since IA32_PEBS_ENABLE and MSR_PEBS_DATA_CFG MSRs are no longer existed
for arch-PEBS, arch-PEBS doesn't need to manipulate these MSRs. Thus add
a simple pair of __intel_pmu_pebs_enable/disable() callbacks for
arch-PEBS.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20251029102136.61364-6-dapeng1.mi@linux.intel.com

...

This commit is contained in:

Dapeng Mi 2025-10-29 18:21:29 +08:00 • committed by Peter Zijlstra

parent 5e4e355ae7

commit d243d0bb64

5 changed files with 132 additions and 33 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

21

arch/x86/events/core.c

View file

60

arch/x86/events/intel/core.c

View file

52

arch/x86/events/intel/ds.c

View file

25

arch/x86/events/perf_event.h

View file

7

arch/x86/include/asm/perf_event.h

View file