RISC-V: SMP cleanup and new features

This patch series now has evolved to contain several related changes. 1. Updated the assorted cleanup series by Palmer. The original cleanup patch series can be found here. http://lists.infradead.org/pipermail/linux-riscv/2018-August/001232.html 2. Implemented decoupling linux logical CPU ids from hart id. Some of the work has been inspired from ARM64. Tested on QEMU & HighFive Unleashed board with/without SMP enabled. 3. Included Anup's cleanup and IPI stat patch. All the patch series have been combined to avoid conflicts as a lot of common code is changed different patch sets. Atish has mostly addressed review comments and fixed checkpatch errors from Palmer's and Anup's series. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2026-10-14 05:55:17 +00:00 · 2018-10-22 17:39:29 -07:00 · 2018-10-22 17:39:29 -07:00 · d26c4bbf99
commit d26c4bbf99
parent a6de21baf6 8b20d2db0a
12 changed files with 259 additions and 70 deletions
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
--- a/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
--- a/drivers/clocksource/riscv_timer.c
+++ b/drivers/clocksource/riscv_timer.c
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c