drm/i915: Enable PCH FIFO underruns later on HSW+

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As we did for ILK/SNB/IVB, move the PCH FIFO underrun enable to happen
after the encoder enable on HSW+. And again, for symmetry, move the
the disable to happen before encoder disable.

I've left out the vblank wait before the enable here because I don't
know if it's needed or not. Actually I don't know if this entire
change is needed as I don't have a HSW/BDW with VGA output.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446146763-31821-5-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

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Ville Syrjälä 2015-10-29 21:25:53 +02:00

parent 37ca8d4ccd

commit d2d65408cc

1 changed files with 9 additions and 7 deletions

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drivers/gpu/drm/i915/intel_display.c

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