perf/x86/intel: Add core PMU support for DMR

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This patch enables core PMU features for Diamond Rapids (Panther Cove
microarchitecture), including Panther Cove specific counter and PEBS
constraints, a new cache events ID table, and the model-specific OMR
events extra registers table.

For detailed information about counter constraints, please refer to
section 16.3 "COUNTER RESTRICTIONS" in the ISE documentation.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260114011750.350569-4-dapeng1.mi@linux.intel.com

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Dapeng Mi 2026-01-14 09:17:46 +08:00 • committed by Peter Zijlstra

parent d2bdcde962

commit d345b6bb88

3 changed files with 207 additions and 1 deletions

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179

arch/x86/events/intel/core.c

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27

arch/x86/events/intel/ds.c

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2

arch/x86/events/perf_event.h

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