ARM: 8682/1: V7M: Set cacheid iff DminLine or IminLine is nonzero

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Cache support is optional feature in M-class cores, thus DminLine or
IminLine of Cache Type Register is zero if caches are not implemented,
but we check the whole CTR which has other features encoded there.
Let's be more precise and check for DminLine and IminLine of CTR
before we set cacheid.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

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Vladimir Murzin 2017-06-12 13:35:52 +01:00 • committed by Russell King

parent bbeedfda8e

commit d360a687d9

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arch/arm/kernel/setup.c

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