arm64: dts: qcom: glymur: Drop fake PCIe phy 3B

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According to user manual / programming guide there is no separate PCIe
phy 3A and 3B, but one 8-lane QMP PCIe Gen5 PHY which consists of two
4-lane blocks.  This is also visible in memory map, where the 0xf00000
is marked as the main block with additional sub blocks for each 4-lane
phys.

Describing the sub phys without the rest is not correct from hardware
description, even if it works.

Link: https://lore.kernel.org/r/20260420-optimistic-unnatural-stingray-80da35@quoll/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260609141608.354186-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

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Krzysztof Kozlowski 2026-06-09 16:16:09 +02:00 • committed by Bjorn Andersson

parent 5d7ebb1f36

commit d3ca4252d2

2 changed files with 1 additions and 43 deletions

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arch/arm64/boot/dts/qcom/glymur-crd.dtsi

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arch/arm64/boot/dts/qcom/glymur.dtsi

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