drm/i915/dg2: Add HDMI pixel clock frequencies 267.30 and 319.89 MHz

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Add snps phy table values for HDMI pixel clocks 267.30 MHz and
319.89 MHz. Values are based on the Bspec algorithm for
PLL programming for HDMI.

Cc: stable@vger.kernel.org
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8008
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230223043619.3941382-1-ankit.k.nautiyal@intel.com

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Ankit Nautiyal 2023-02-23 10:06:19 +05:30 • committed by Uma Shankar

parent cb42e8ede5

commit d46746b8b1

1 changed files with 62 additions and 0 deletions

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drivers/gpu/drm/i915/display/intel_snps_phy.c

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