riscv: dts: starfive: Add JH7100 cache controller

Browse source

The StarFive JH7100 SoC also features the SiFive L2 cache controller,
so add the device tree nodes for it.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

...

This commit is contained in:

Emil Renner Berthing 2023-11-30 16:19:28 +01:00 • committed by Conor Dooley

parent ba0074972e

commit d4b95c445c

1 changed files with 13 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

13

arch/riscv/boot/dts/starfive/jh7100.dtsi

View file