clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2

Browse source

Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't
know the relation between this clock and RGMII Ethernet. It turns out
that fclk_div2 is used as "timing adjustment clock" to generate the RX
delay on the MAC side - which was enabled by u-boot on Odriod-C1. When
using the RX delay on the PHY side or not using a RX delay at all then
this clock can be disabled.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200620161422.24114-1-martin.blumenstingl@googlemail.com

...

This commit is contained in:

Martin Blumenstingl 2020-06-20 18:14:22 +02:00 • committed by Jerome Brunet

parent 2f1efa5340

commit d4db5721f3

1 changed files with 0 additions and 7 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

7

drivers/clk/meson/meson8b.c

View file